DESIGN AND SIMULATION OF A HOMODYNE FM RECEIVER BASED ON A FRACTIONAL ORDER PLL

Abstract

This thesis explores the design and performance analysis of Phase-Locked Loop (PLL) circuits in FM communication systems, specifically in VHF. The detailed design and sizing of essential circuit components combine theoretical analysis and practical implementation through simulation. Key aspects covered, such as phase detectors, low-pass filters, and voltage-controlled oscillators (VCOs), ensure a comprehensive understanding of their roles and performance metrics. Time-domain measurements, evaluating the PLL's behavior in open-loop and closed-loop configurations, are conducted. The simulations reveal transient responses followed by a steady-state regime, highlighting the PLL's ability to effectively demodulate received FM signals. The results show that in a closed-loop, parasitic voltages are reduced, and PLL stability is established. Although fractional-order PLL designs were not included due to time constraints, the study provides valuable insights into traditional integer-order PLL circuits. This study serves as a solid foundation for future advancements in FM communication systems, emphasizing the importance of assisted design and precise simulation in improving PLL performance.