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COMPREHENSIVE EXPLORATION AND DESIGN IMPLEMENTATION OF AN FPGA-BASED CONVOLUTIONAL NEURAL NETWORK

dc.contributor.authorFekir, Mohamed
dc.contributor.authorMoualdia, Abdelhafid
dc.date.accessioned2024-11-26T09:36:21Z
dc.date.available2024-11-26T09:36:21Z
dc.date.issued2023-10
dc.description.abstractThis paper explores the use of a cost-effective Field Programmable Gate Array (FPGA) to deploy a Convolutional Neural Network (CNN) while ensuring optimal performance. CNNs are a type of Artificial Neural Network (ANN) designed for image processing and computer vision tasks. They are inspired by the intricate structure of the biological visual cortex and can identify complex patterns in large datasets. Compared to traditional deep learning models, CNNs are better at pattern recognition and require fewer computational resources for training and deployment. However, implementing CNNs on an FPGA presents challenges that require a thorough evaluation of performance metrics. Our research has two main objectives: first, we focus on training the CNN model to achieve high accuracy, and second, we optimize the hardware design to suit the FPGA platform. We use the LeNet5 CNN model and the Modified National Institute of Standards (MNIST) dataset for experimentation. High-level synthesis (HLS) is used to assess the CNN's performance on a VC707 FPGA board. Our results show an accuracy rate of over 97% and a latency of 299.3µs, demonstrating the effectiveness of our FPGA implementation in achieving robust CNN performancefr_FR
dc.identifier.citationTechnologiefr_FR
dc.identifier.govdocA75.57
dc.identifier.urihttps://dspace.univ-medea.dz/handle/123456789/12323
dc.language.isoenfr_FR
dc.subjectOptimizationfr_FR
dc.subjectConvolutional neural networks (CNNs)fr_FR
dc.subjectField Programmable Gate Array (FPGAfr_FR
dc.subjecthardware implementationfr_FR
dc.titleCOMPREHENSIVE EXPLORATION AND DESIGN IMPLEMENTATION OF AN FPGA-BASED CONVOLUTIONAL NEURAL NETWORKfr_FR
dc.typeArticlefr_FR

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